The present invention relates to a level shifter that converts a digital signal having a predetermined voltage level to a digital signal having a voltage different therefrom and outputs the converted digital signal.
FIG. 2 is a configuration diagram of a conventional or prior art level shifter described in a patent document 1 (Japanese Unexamined Patent Publication No. 2006-135712).
The level shifter comprises P-channel MOS type transistors P1 through P6, and N-channel MOS type transistors N1 through N4.
The sources of the transistors P1 and P2 are connected to a relatively higher source potential VDD. The gates thereof are connected to nodes n2 and n1, and the drains thereof are connected to nodes n3 and n4, respectively. The sources of the transistors P3 and P4 are respectively connected to the nodes n3 and n4, and the drains thereof are respectively connected to a ground potential GND via the transistors N1 and N2. The sources of the transistors P5 and P6 are respectively connected to the nodes n3 and n4, and the drains thereof are respectively connected to the ground potential GND via the transistors N3 and N4. Incidentally, a connecting point of the transistors P5 and N3 is configured as the node n1, and a connecting point of the transistors P6 and N4 is configured as the node n2.
The gates of the transistors P3, P5, N1 and N3 are supplied with a digital input signal IN corresponding to a relatively lower source potential VCC in common. An input signal INB obtained by inverting the input signal IN is supplied to the gates of the transistors P4, P6, N2 and N4 in common. A digital output signal OUT corresponding to the source potential VDD is outputted from a connecting point of the transistors P3 and N1. An output signal OUTB obtained by inverting the output signal OUT is outputted from a connecting point of the transistors P4 and N2.
The operation of the level shifter will next be explained.
Firstly, when the input signals IN and INB are stable at levels “L” and “H” respectively, the transistors P3, P5, N2 and N4 are held ON and the transistors P4, PG, N1 and N3 are held OFF. Thus, the node n2 is brought to “L” so that the transistor P1 is turned ON, and the node n1 is brought to “H” so that the transistor P2 is turned OFF. Signals of “H” and “L” having levels corresponding to the source potential VDD are respectively outputted as the output signals OUT and OUTB.
Now, when the input signal IN changes from “L” to “H” and the input signal INB changes from “H” to “L”, respectively, the transistors P3, P5, N2 and N4 are changed to OFF and the transistors P4, P6, N1 and N3 are changed to ON, respectively. With the turning ON and OFF of the transistors N1 and P3 respectively, the output signal OUT changes from “H” to “L”. With the turning ON and OFF of the transistors N3 and P5 respectively, the potential of the node n1 is reduced to the ground potential GND.
On the other hand, since the potential of the node n2 depends upon the state (i.e., the potential of the node n1) of the transistor P2 even though the transistors N4 and P6 are respectively brought to OFF and ON, its potential remains unchanged until the potential of the node n1 is sufficiently lowered. When the potential of the node n1 is sufficiently reduced, the transistor P2 is turned ON, so that the potential of the node n4 rises to the source potential VDD. Thus, the output signal OUTB changes from “L” to “H”. The potential of the node n2 also rises so that the transistor P1 is turned OFF.
Next, when the input signal IN changes from “H” to “L” and the input signal INB changes from “L” to “H”, respectively, the transistors P3, P5, N2 and N4 are changed to ON and the transistors P4, P6, N1 and N3 are changed to OFF, respectively. With the turning ON and OFF of the transistors N2 and P4 respectively, the output signal OUTB changes from “H” to “L”. With the turning ON and OFF of the transistors N4 and P6 respectively, the potential of the node n2 is reduced to the ground potential GND.
On the other hand, since the potential of the node n1 depends on a state (i.e., the potential of the node n2) of the transistor P1 even when the transistors N3 and P5 are respectively brought to OFF and ON, the potential thereof remains unchanged until the potential of the node n2 is sufficiently reduced. When the potential of the node n2 is sufficiently reduced, the transistor P1 is turned ON so that the potential of the node n3 rises to the source potential VDD. Thus, the output signal OUT changes from “L” to “H”. The potential of the node n1 also rises so that the transistor P2 is turned OFF.
Since the output circuits for outputting the output signals OUT and OUTB to external circuits respectively, and the nodes n1 and n2 for controlling internal states are separated from one another in the level shifter, the nodes n1 and n2 can respectively be brought to “L” by voltage drops developed across source-to-drain resistances of the transistors P5 and P6 regardless of the sizes of the transistors P1, P2, N3 and N4. As a result, drive capacities of the transistors P1 through P4, N1 and N2 can be enhanced, thus making it possible to increase an operating speed.
FIG. 3 is a configuration diagram showing one example of a system using a level shifter.
The system shows an example in which a signal from a peripheral circuit operated at a low source potential VCC is inputted to a microcomputer operated at a relatively high source potential VDD. A level shifter is provided at an input unit of the microcomputer. A digital signal IN of a VCC level outputted from the peripheral circuit is supplied to the level shifter, where it is converted into a digital signal of a VDD level, followed by being inputted to a core circuit of the microcomputer.
Such a system needs not to always operate depending upon the type of peripheral circuit. There is also known one that may operate only when started up from the microcomputer. In such a case, such a peripheral circuit that is brought to an active state only when started up from the microcomputer and brought to a standby state in which it has ceased operating when the operation thereof is unnecessary, has been used to reduce power consumption.
In recent years, the threshold voltage of each transistor has been lowered according to a strong demand for a reduction in power and a reduction in source voltage, whereby an off-leakage current in a standby state turns into a problem. As a method of reducing the off-leakage current, there has been adopted a method for switching a source potential VCC to a ground potential GND to stop the supply of power to a peripheral circuit during standby. In such a case, the potential of a digital signal IN supplied from the peripheral circuit to a level shifter is also switched to the ground potential GND.
When the input signals IN and INB are both brought to the ground potential GND in the level shifter shown in FIG. 2, the transistors P3 through P6 are turned ON simultaneously, and the transistors N1 through N4 are turned OFF simultaneously. Therefore, the transistors P1 and P2 are turned OFF simultaneously, and the output signals OUT and OUTB and the potentials of the nodes n1 and n2 are respectively brought to an instable intermediate potential, thereby causing through currents that flow from the transistors P1 and P2 to the transistors N1 through N4. A problem arises in that degradation in the lifetime of each transistor occurs in addition to the generation of needless power consumption due to the through currents, thereby impairing reliability.